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Parallel Computation of Sparse Rulers

This article explains the sparse ruler problem, two parallel codes for computing sparse rulers, and some new results that reveal a surprising "gap" behavior for solutions to the sparse ruler problem....

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Intel® Xeon® Processor E7 V2 Family Technical Overview

Download PDF Contents1. Executive Summary 2. Introduction 3. Intel® Xeon® processor E7 V2 family enhancements  3.1 Intel® C104/102 Scalable Memory Buffer  3.2 Intel® Secure Key (DRNG)  3.3 Intel® OS...

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Intel® Xeon® Processor E7 v2 Family

 Based on Intel® Core™ microarchitecture (formerly codenamed Ivy Bridge) and manufactured on 22-nanometer process technology, the Intel® Xeon® Processor E7 V2 Family processors provide significant...

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Selective Use of gatherhint/scatterhint Instructions

Compiler Methodology for Intel® MIC ArchitectureSelective Use of gatherhint/scatterhint InstructionsOverviewThe -opt-gather-scatter-unroll=<N> compiler option can be used to generate...

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Diagnostic 15038: remark: loop was not vectorized: conditional assignment to...

Causes:1. A loop contains a conditional statement 2. The conditional statement is controlling the assignment of a scalar value. 3. The logic of the assignment is such that the value of the scalar at...

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Flow Graph Designer

What If Home | Product Overview | System Requirements | Useful Links | Development Team | Discussion ForumThis download is available under the What If Pre-Release License Agreement Product OverviewFlow...

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Resource Guide for People Investigating the Intel® Xeon Phi™ Coprocessor

This article identifies resources for anyone investigating the value to their organization of the Intel® Xeon Phi™ coprocessor, which is based on the Intel® Many Integrated Core (Intel® MIC)...

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Intel® Software Development Tools 2015 Beta

Intel® Software Development Tools 2015 Beta What's New in the 2015 BetaThis suite of products brings together exciting new technologies along with improvements to Intel’s existing software development...

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A Parallel Stable Sort Using C++11 for TBB, Cilk Plus, and OpenMP

This article describes a parallel merge sort code, and why it is more scalable than parallel quicksort or parallel samplesort. The code relies on the C++11 “move” semantics. It also points out a...

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Power Management States: P-States, C-States, and Package C-States

(For a PDF version of this article, download the attachment.)ContentsPreface: What, Why and from Where. 1Chapter 1: Introduction and inquiring minds. 2Chapter 2: P-States, Reducing power consumption...

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List of Useful Power and Power Management Articles, Blogs and References

INTRODUCTION AND PURPOSE:This article endeavors to provide a single point of reference to Power Management blogs, articles and other resources relevant to the Intel® Xeon Phi™ coprocessor.There are...

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GCC* 4.9 OpenMP code cannot be linked with Intel® OpenMP runtime

GCC* 4.9 was released on April 22, 2014.  This release now supports Version 4.0 of the OpenMP* specification for the C and C++ compilers.  The interface between the compilers and the GCC OpenMP runtime...

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Using Intel® Math Kernel Library with MathWorks* MATLAB* on Intel® Xeon Phi™...

OverviewThis guide is intended to help developers use the latest version of Intel® Math Kernel Library (Intel® MKL) with MathWorks* MATLAB* on Intel® Xeon Phi™ Coprocessor System.Intel MKL is a...

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Controlling floating-point modes when using Intel® Threading Building Blocks

Intel® Threading Building Blocks (Intel® TBB) 4.2 Update 4 introduced enhanced support for managing floating-pointing settings. Floating-point settings can now be specified at the invocation of most...

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Compiler, Architecture and Tools Conference

December 1st, 2014 Intel Development Center, Haifa, Israel Endorsed by the HiPEAC Network of Excellencehttp://software.intel.com/compilerconf2014...

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Using Intel® Advisor XE to Observe Memory Accesses Dynamically

Intel® Advisor XE is the premiere tool from Intel for helping to parallelize your code, but it can also be used in other ways. For example, you can take advantage of the Intel Advisor XE special...

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WRF Conus2.5km on Intel® Xeon Phi™ Coprocessors and Intel® Xeon® processors...

OverviewThis document demonstrates the best methods to obtain, build and run the WRF model on multiple nodes in symmetric mode on Intel® Xeon Phi™ Coprocessors and Intel® Xeon processors. This document...

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Resource Guide for People Investigating the Intel® Xeon Phi™ Coprocessor

This article identifies resources for anyone investigating the value to their organization of the Intel® Xeon Phi™ coprocessor, which is based on the Intel® Many Integrated Core (Intel® MIC)...

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WRF Conus2.5km on Intel® Xeon Phi™ Coprocessors and Intel® Xeon® processors...

OverviewThis document demonstrates the best methods to obtain, build and run the WRF model on multiple nodes in symmetric mode on Intel® Xeon Phi™ Coprocessors and Intel® Xeon processors. This document...

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WRF Conus12km on Intel® Xeon Phi™ Coprocessors and Intel® Xeon® Processors

I. OverviewThis document demonstrates the best methods to obtain, build, and run the Weather Research and Forecasting (WRF) model on an Intel® Xeon® processor-based server in native mode on a single...

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